An Efficient Pipelined Complex Multiplier
نویسندگان
چکیده
In this paper, we propose a pipeline scheme for efficient realization of a complex multiplier using distributed arithmetic. The pipelined multiplier consists of one conventional multiplier that is multiplexed and some small additional circuitry on the boundary. The proposed scheme reduces the chip area as well as the interconnections by nearly half compared to a conventional complex multiplier. The pipelined multiplier is efficient in terms of chip area and interconnect, which reduces the power consumption.
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